Integrated circuit memories were originally designed to merely store data which could be retrieved at a later time. As such, the memories contained memory cells which were capable of being written to and read from. As the computer and communications industries continued to developed, memory circuits have evolved which contain special modes of operation. These modes have been designed to meet market demands for memory circuits which can be accessed and/or operated in a manner different than other memory circuits.
One type of memory circuit, a dynamic random access memory (DRAM), typically comprise a memory array having memory cells arranged in rows and columns. Individual memory cells can be accessed by using external address lines, and memory control circuitry is provided to control the reading and writing operations of the DRAM. Further, additional memories can be included in the integrated circuit to create a multi-port memory circuit. For example, a multi-port memory is described in U.S. Pat. No. 4,891,794 issued to Hush et al. entitled "Three Port Random Access Memory" which is assigned to the assignee of the present application and is incorporated herein by reference.
Multi-port random access memories (RAM) are substantially faster than standard RAM and commonly referred to as video random access memories (VRAM) because of their effectiveness in video systems. In its simplest form, the multi-port memory includes a DRAM array, control circuitry, and a serial access memory (SAM). The SAM is essentially a long shift register which can receive a block of data from the DRAM and serially shift the data out through a data port. The SAM can also serially shift data in through the serial port and transfer the data to the DRAM. Other multi-port memories may include a different number of serial access memories. The memory control circuitry in a multi-port memory is used to control data transfers between the DRAM and the SAM.
In addition to different memory circuits, several different modes of accessing and reading the memory cells of the DRAM have been developed, including Page Mode, Extended Data Output (EDO), and Burst EDO. While the basic hardware building blocks for each of these memories are essentially the same, subtle differences exist between the manufactured memories to provide for the different modes of operation. Further, each memory mode has a set of unique operating parameters which a packaged memory circuit must operate within. If any of these parameters are not achieved, the memory circuit must be discarded as scrap. Scrapping a memory circuit which functions properly, merely because it has a characteristic which falls outside the parameters of a specification, is economically unsatisfactory. Additionally, the market demand for memories having different modes of operation fluctuate with the demand and development of different peripheral technologies. A production decision to manufacture memory circuits to meet forecasted demands for a particular operating mode may result in memory circuits which are actually not in demand if the forecast is inaccurate. As such, the market price for the memory circuits will be reduced from what it would have been had the forecast been accurate.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory circuit which can be changed after final packaging processes such that the mode of operation can be changed. This "back end" operation allows the original operating mode of the memory circuit to be disabled and a new mode enabled. Production scrap can, therefore, be reduced by changing the mode of completed memories to a mode with different operating parameters.